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ram mapping 16*8 led controller driver with keyscan HT16K33 revision: v.1.10 date: ? a? 1?? ? 011 ?a? 1?? ? 011
rev. 1.10 pb ?a? 1?? ? 011 rev. 1.10 i ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan table of contents eate latons eneal eston lo aa n ssnent n eston oate ntenal connetons bsolte a atns c caatests c caatests c caatests tn aas ntonal eston power-on reset ....................................................................................................................... 8 standb? ?ode .......................................................................................................................... 8 wake-up ................................................................................................................................... 9 s?stem setup register ............................................................................................... 10 row/int set register ................................................................................................. 10 displa? setup register ............................................................................................... 11 s?stem oscillator ........................................................................................................ 1? displa? data address pointer .................................................................................... 1? ke? data address pointer .......................................................................................... 1? register information address pointer ....................................................................... 1? row driver outputs ..................................................................................................... 1? column driver outputs ............................................................................................... 1? displa? ?emor? ra? structure .............................................................................. 13 led drive mode waveforms and scanning is as follows: ...................................................... 13 digital dimming data input ........................................................................................ 15 ke?scan ........................................................................................................................ 17 ke? scan timing ...................................................................................................................... 18 ke? scan & int timing ............................................................................................................ 18 ke? data ?emor? ra? structure ........................................................................... ?1 key ?atrix configuration ................................................................................. ?? when p ressing three or more times is assumed: ................................................................... ?? when pressing twice or more times is assumed: ................................................................... ?? ke? matrix combination with ?8 pin package ......................................................................... ?3 ke? matrix combination with ?4 pin package ......................................................................... ?4
rev. 1.10 ii ?a? 1?? ? 011 rev. 1.10 1 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan ke? matrix combination with ?0 pin package ......................................................................... ?4 i 2 c serial interface ....................................................................................................... 25 data validit? ............................................................................................................................ ?5 start and stop conditions ................................................................................................. ?5 b?te format ............................................................................................................................. ?5 acknowledge ............................................................................................................... 26 slave addressing ................................................................................................................... ?? write operation ............................................................................................................ 28 b?te write operation ............................................................................................................... ?8 page write operation .............................................................................................................. ?8 read operation ............................................................................................................ 29 b?te read operation ................................................................................................................ ?9 page read operation ............................................................................................................... ?9 command summary ................................................................................................... 30 HT16K33 operation fow chart ................................................................................................ 3? application circuit ...................................................................................................... 34 led matrix circuit ....................................................................................................... 37 package information ................................................................................................... 38 ? 0-pin sop (300mil) outline dimensions .............................................................................. 38 ? 4-pin sop (300mil) outline dimensions .............................................................................. 39 ? 8-pin sop (300mil) outline dimensions .............................................................................. 40 reel dimensions .................................................................................................................... 41 carrier tape dimensions ........................................................................................................ 4?
rev. 1.10 ii ?a? 1?? ? 011 rev. 1.10 1 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan feature operating voltage: 4.5v~5.5v integrated rc oscillator i 2 c-bus interface 16*8 bits ram for display data storage max. 16 x 8 patterns, 16 segments and 8 commons r/w address auto increment max. 13 x 3 matrix key scanning 16-step dimming circuit selection of 20/24/28-pin sop package types applications industrial control indicators digital clocks, thermometers, counters, multimeters combo sets vcr sets instrumentation readouts other consumer applications led displays general description the HT16K33 is a memory mapping and multi-function led controller driver. the max. display segment numbers in the device is 128 patterns (16 segments and 8 commons) with a 13*3 (max.) matrix key scan circuit. the software configuration features of the HT16K33 makes it suitable for multiple led applications including led modules and display subsystems. the HT16K33 is compatible with most microcontrollers and communicates via a two-line bidirectional i 2 c-bus.
rev. 1.10 ? ?a? 1?? ? 011 rev. 1.10 3 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan block diagram row driver output interrupt function output ke? data input device address data input displa? ra? 1?*8bits timing generator i ? c controller co? 0 / ad co? 1 / ks0 co? ? / ks1 co? 3 / ks? row0/ a? vdd vss sda scl power_on reset co?5 co?? co?7 co?4 por por row1/ a1 row1?/ k10 row15 /k13/ int ke? data ra? 13*3bits por row13/ k11 row14/ k1? row?/ a0 row3/ k1 internal rc oscillator common scan output ke? scan output device address source output a[?: 0 ] por por por por
rev. 1.10 ? ?a? 1?? ? 011 rev. 1.10 3 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan pin assignment

HT16K33 20 sop-a

HT16K33 24 sop-a

HT16K33 28 sop-a
rev. 1.10 4 ?a? 1?? ? 011 rev. 1.10 5 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan pin description pin name type description sda i/o i ? c interface serial data input/output scl i i ? c interface serial clock input v dd positive power suppl? for logic circuit v ss negative power suppl? for logic circuit? ground co?0/ad o common output pin? active low during displa? also used as device address source output pin? active high during power on reset and ke? scan co?1/ks0~co?3/ks? o common output pin? active low when displa?ing also used as the ke? source output pin? active high during ke? scan operation co?4~co?7 o common outputs pin? active low during displa? . 28 pin package row0/a?~row?/a0 i/o row output pin? active high when displa?ing also used as the device address data input pin ? internal pull-low during power on reset and during ke? scan operation row3/k1~row14/k1? i/o row outputs pin? active high during displa? . also used as the ke? data input pin? internal pull-low during ke? scan operation row15/k13 /int i/o when the int/row bit of row/int set register is set to 0 ? this pin become a row driver output pin? active high when displa?ing? and ke? data input during ke? scan operation. when the int/row bit of row/int set register is set to 1 ? this pin become interrupt signal (int) output pin. int pin output active-high when the act bit of the row/int setup register is set to 0. int pin output active-high when the act bit of the row/int register is set to 1. 24 pin package row0/a1~row1/a0 i/o row output pin? active high when displa?ing also used as the device address data input pin ? internal pull-low during a power on reset and during a ke? scan operation row?/k1~row10/k9 i/o row outputs pin? active high when displa?ing also used as the ke ? data inputs pin? internal pull-low during a ke ? scan operation row11/k10/int i/o when the int/row bit of row/int set register is set to 0 ? this pin become a row driver output ? active high when displa?ing? and ke? data input during a ke?scan operation when the int/row bit of row/int set register is set to 1 ? this pin become an interrupt signal (int) output pin. int pin output active-high when the act bit of the row/int setup register is set to 0. int pin output active-high when the act bit of the row/int setup register is set to 1. 20 pin package row0/k1~row?/k7 i/o row output pin? active high when displa?ing also used as the ke ? data inputs pin? internal pull-low during a ke ? scan operation row7/k8 /int i/o when the int/row bit of the row/int setup register is set to 0 ? this pin become a row driver output ? active high when displa ? ing? and ke? data input during a ke? scan operation when the int/row bit of the row/int set register is set to 1 ? this pin become an interrupt (int) signal output pin int pin output active-high when the act bit of row/int setup register is set to 0 int pin output active-high when the act bit of the row/int set register is set to 1
rev. 1.10 4 ?a? 1?? ? 011 rev. 1.10 5 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan approximate internal connections scl ? sda ( for schmit trigger t?pe ) row ? / a 0 ~ row 0 / a ? ? row 3 / k 1 ~ row 14 / k 1? co? 0 / ad ? co? 1 / ks 0 ~ co? 3 / ks ? vss vdd co? 4 ~ co? 7 row 15/ k 13 / int vdd vss r vss vdd vss vdd r vss absolute maximum ratings supply voltage ................................................................................................ v ss -0.3v to v ss +6.5v input voltage .................................................................................................. v ss -0.3v to v dd +0.3v storage temperature .................................................................................................. -50 c to 125c operating temperature ................................................................................................ -40 c to 85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.10 ? ?a? 1?? ? 011 rev. 1.10 7 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan d.c. characteristics v dd =4.5~5.5v; ta=25c (unless otherwise specifed) symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 4.5 5 5.5 v i dd operating current 5 no load? normal operation? int/row bit is set to 0 1 ? ma i stb standb? current 5 no load? standb? mode 1 10 a v ih input high voltage 5 sda?scl 0.7v dd v dd v v il input low voltage 5 sda? scl 0 0.3v dd v i il input leakage current v in = v ss or v dd -1 1 a r pl input pull-low resistor 5 row3/k1~row15/k13? row0/a?~row? /a0 ke? scan during ?50 k i ol1 low level output current 5 v ol =0.4v; sda ? ma i ol? row sink current 5 v ol =0.4v ? int pin ? ma i oh1 row source current 5 v oh =v dd -?v ? (row0~row15 pin) -?0 -?5 -40 ma v oh =v dd -3v ? (row0~row15 pin ) -?5 -30 -50 ma i math row source current tolerance 5 v oh =v dd -3v ? (row0~row15 pin ) 5 % i ol3 co? sink current 5 v ol =0.3v ? (co?0~co?7 pin) 1?0 ?00 ma i oh? co? source current 5 v oh =v dd -?v ? (co?0~co?3 pin) -?0 -?5 -40 ma a.c. characteristics v dd =4.5~5.5v; ta=25c (unless otherwise specifed) symbol parameter test condition min. typ. max. unit v dd condition t led led frame time 5 1/9 dut? 7.? 9.5 11.4 ms t off v dd off time v dd drop down to 0v ?0 ms t sr v dd slew rate 0.05 v/ms 1rwh?iwkh3rzhurq5hvhwwlplqfrqglwlrqvduhqrwvdwlvhglqwkhsrzhu?1?))vhtxhqfhwkhlqwhuqdo power on reset circuit will not operate normally. 2. i f vdd drops below the minimum voltage of the operating voltage spec. during operating, the power on 5hvhwwlplfrglwlrvpxvwdovrehvdwlvhg7kdwlv9pxvwgurswr9dguhpdldw9irupvpl before rising to the normal operating voltage.
rev. 1.10 ? ?a? 1?? ? 011 rev. 1.10 7 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan a.c. characteristics symbol parameter test condition min. max. unit condition f scl clock frequenc? 400 khz t buf bus free time time in which the bus must be free before a new transmission can start 1.3 s t hd; sta start condition hold time after this period, the frst clock pulse is generated 0.? s t low scl low time 1.3 s t high scl high time 0.? s t su; sta start condition set-up time onl? relevant for repeated start condition. 0.? s t hd; dat data hold time 0 s t su; dat data set-up time 100 ns t r rise time note 0.3 s t f fall time note 0.3 s t su; sto stop condition set-up time 0.? s t aa output valid from clock 0.9 s t sp input filter time constant (sda and scl pins) noise suppression time 50 ns note: these parameters are periodically sampled but not 100% tested. timing diagrams i 2 c timing sda scl t f t hd:sda t low t r t hd:dat t su:dat t high t su:sta t hd:sta s sr t sp t su:sto p t buf s t aa sda out power-on reset timing
rev. 1.10 8 ?a? 1?? ? 011 rev. 1.10 9 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan functional description power-on reset when power is applied, the ic is initialised by an internal power-on reset circuit. the status of the internal circuit after initialisation is as follows: system oscillator will be in an off state com0~com3 outputs are set to v dd com4~com7 outputs will be high impedance all rows pins are changed input pins led display is in the off state. key scan stopped the combined row/int pins are setup as row outputs dimming is set to 16/16duty data transfers on the i 2 c-bus should be avoided for 1 ms following a power-on to allow completion of the reset action. standby mode in the standby mode, the HT16K33 can not accept input commands nor write data to the display ram except using the system setup command. if the standby mode is selected with the s bit of the system setup register set to 0, the status of the standby model is as follows: system oscillator will be in the off state com0~com3 outputs are set to vdd com4~com7 outputs will be high impedance led display is in the off state. key scan stopped all key data and int fags are cleared until the standby mode is canceled. if the key matrix is activated (any key) or the s bit of the system setup register is set to 1, the standby mode will be canceled and will cause the device to wake-up. if the int/row bit of the row/int setup register is set to 0, all rows pins are changed to input pins. if the int/row bit of the row/int setup register is set to 1: all rows pins are changed to input pins except for the int pin (output). the int pin output will remain at a high level when the act bit of the row/int setup register is set to 0. the int pin output remains at a low level when the act bit of the row/int setup register is set to 1.
rev. 1.10 8 ?a? 1?? ? 011 rev. 1.10 9 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan wake-up wake-up by a key press from any key or by setting the s bit of the system setup register to 1. a key scan will then be performed. the system oscillator restarts for normal operation. the previous display data output will be updated by each mode command set. the relationship between the wake-up and any key press is shown as follows: wake-up standb? mode command set from ?cu read ke? data command set from ?cu int flag or int pin output an? ke? press release key ? frame c?cle normal active status ht1?k33 operation status standb? status press ? frame c?cle < ? frame c?cle release key normal active status press release (when the act bit is set to 1) 1. ke? data are updated ?. slave address are updated 1. ke? data are updated ?. slave address are updated when after the ke? data has been read?clears the ke? data ra?. when after the ke? data has been read?clears the ke? data ra?. in the sleep mode, ks0-k1 or ks1-k1 can not wake-up the device when the ks2-k1 keys are nhswsuhvvhggr,wlvdsurklelwhgdssolfdwlrdvvkrlwkhiroorlxuh co? 1 / ks 0 co? ? / ks 1 co? 3 / ks ? row 0 / k 1 row 1 / k ? row ? / k ? these ke? can not walk - up ic keep press down the ke?
rev. 1.10 10 ?a? 1?? ? 011 rev. 1.10 11 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan system setup register the system setup register confgures system operation or standby for the HT16K33. the internal system oscillator is enabled when the s bit of the system setup register is set to 1. the internal system clock is disabled and the device will enter the standby mode when the s bit of the system setup register is set to 0. before the standby mode command is sent, it is strongly recommended to read the key data frst. the system setup register command is shown as follows: name command / address / data option description def. d15 d14 d13 d12 d11 d10 d9 d8 s?stem set 0 0 1 0 x x x s {s} write onl? defnes internal system oscillator on/off {0}:turn off s ? stem oscillator (standb? mode) {1}:turn on s ? stem oscillator (normal operation mode) ?0h row/int set register the row/int setup register can be set to either an led row output, or an int logic output. the int output is selected when the row/int set register is set to 1. the row output is selected when the row/int set register is set to 0. the int logic output can be confgured as an int output level controlled by the keyscan circuitry and controlled through the 2-wire interface. the int output is active-low when the act bit of row/int set register is set to 0. the int output is active-high when the act bit of row/int set t register is set to 1. the row/int setup register command is shown as follows: name command / address / data option description def. d15 d14 d13 d12 d11 d10 d9 d8 row/int set 1 0 1 0 x x act row/ int {act? row/int } write onl? defines int/row output pin select and int pin output active level status. {x 0}: int/row output pin is set to row driver output. {0? 1}: int/row output pin is set to int output ? active low. {1? 1}: int/row output pin is set to int output ? active high. a0h
rev. 1.10 10 ?a? 1?? ? 011 rev. 1.10 11 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan display setup register the display setup register configures the led display on/off and the blinking frequency for the HT16K33. the led display is enabled when the d bit of the display setup register is set to 1. the led display is disabled when the d bit of the display setup register is set to 0. in the display disable status, all row outputs are hi-impedance and all com outputs are high- impedance during the display period. in the display disable status, all rows are changed to an input status and the com0~com3 continues scanning and com4~com7 outputs are high-impedance during the keyscan period. the display blinking capabilities of the HT16K33 are very versatile. the whole display can be blinked at frequencies selected by the blink command. the blinking frequencies are integer multiples of the system frequency; the ratios between the system oscillator and the blinking frequencies depend upon the mode in which the device is operating, is as follows: blinking frequency = 2hz example of waveform for blinker the display setup register command is as follows: name command / address / data option description def. d15 d14 d13 d12 d11 d10 d9 d8 displa? set 1 0 0 0 x b1 b0 d {d} write onl? defnes display on/off status. {0}: displa? off {1}: displa? on 80h {b1?b0} write onl? defnes the blinking frequency {0?0} = blinking off {0?1} = ?hz {1?0} = 1hz {1?1} = 0.5hz
rev. 1.10 1? ?a? 1?? ? 011 rev. 1.10 13 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan system oscillator the internal logic and the led drive signals of the HT16K33 are timed by the integrated rc oscillator. the system clock frequency determines the led frame frequency. a clock signal must always be supplied to the device; removing the clock may freeze the device if the standby mode command is executed. at initial system power on, the system oscillator is in the stop state. display data address pointer the addressing mechanism for the display ram is implemented using the address pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialisation of the address pointer by the address pointer command. key data address pointer the addressing mechanism for the key data ram is implemented using the address pointer. this allows the loading of an individual key data byte, or a series of key data bytes, into any location of the key data ram. the sequence commences with the initiali s ation of the address pointer by the address pointer command. register information address pointer the addressing mechanism for the register data and interrupt fag information ram is implemented using the address pointer. this allows the loading of an individual register data and interrupt fag data byte, or a series of register data and interrupt fag data bytes, into any location of the register data and interrupt fag information ram. the sequence commences with the initiali s ation of the address pointer by the address pointer command. row driver outputs the l e d drive section includes 16 row outputs row 0 to row15 which should be connected directly to the l e d panel . the row output signals are generated in accordance with the multiplexed column signals and with the data resident in the display latch. when less than 15 row outputs are required the unused row outputs should be left open-circuit. c olumn driver outputs the l e d drive section includes eight column outputs com 0 to com7 which should be connected directly to the l e d panel . the column output signals are generated in accordance with the selected l e d drive mode. when less than 8 column outputs are required the unused column outputs should be left open-circuit.
rev. 1.10 1? ?a? 1?? ? 011 rev. 1.10 13 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan display memory C ram structure the display ram is a static 16 x 8 -bits ram which stores the led data. logic 1 in the ram bit-map indicates the on state of the corresponding led row; similarly, a logic 0 indicates the off state. there is a one-to-one correspondence between the ram addresses and the row outputs, and between the individual bits of a ram word and the column outputs. the following shows the mapping from the ram to the led pattern: com0 row0 row7 row8 row15 co?0 00h 01h co?1 0?h 03h co?? 04h 05h co?3 0?h 07h co?4 08h 09h co?5 0ah 0bh co?? 0ch 0dh co?7 0eh 0fh i 2 c bu s d isplay data transfer format data byte of i 2 c d7 d6 d5 d4 d3 d2 d1 d0 row 7 ? 5 4 3 ? 1 0 15 14 13 1? 11 10 9 8 led drive mode waveforms and scanning is as follows: the HT16K33 allows use of 1/9 duty mode and the combine d row/int pin is set to a row driver output as shown : row3/k1~row15/k13 1040 s 32 s 1024 s co?0 (ad) co?1 (ks0) co?? (ks1) co?3 (ks?) co?4 co?5 co?? co?7 16 s 16 s 1 frame=1056us*9=9.504ms 32 s hi-z hi-z vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss low hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z low low hi hi hi hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z low low low low low low low hi led display period key scan period row0/a?~row?/a0 hi-z
rev. 1.10 14 ?a? 1?? ? 011 rev. 1.10 15 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan k ey scan period e nlargement co?1/ks0 co??/ks1 c0?3/ks? 10?4 s vdd vss vdd vss vdd vss ke? scan period ke? data and slave address are updated input status vdd vss ?5? s row0/a?~row?/a0 ?5? s ?5? s vdd vss c0?4~co?? hi-z hi-z hi-z c0?7 3? s 3? s 1? s vss vdd vdd vss co?0/ad hi-z hi-z hi-z low high high high high ?5? s low hi-z hi-z hi-z hi-z row3/k1~row15/k13 hi-z hi-z note: the row/in combine d pin is set to a row driver output.
rev. 1.10 14 ?a? 1?? ? 011 rev. 1.10 15 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan digital dimming data input the display dimming capabilities of the HT16K33 are very versatile. the whole display can be dimmed using pulse width modulation techniques for the row driver by the dimming command, as shown: d15 d14 d13 d12 d11 d10 d9 d8 row driver output pulse width def. 1 1 1 0 p3 p? p1 p0 1 1 1 0 0 0 0 0 1/1? dut? 1 1 1 0 0 0 0 1 ?/1? dut? 1 1 1 0 0 0 1 0 3/1? dut? 1 1 1 0 0 0 1 1 4/1? dut? 1 1 1 0 0 1 0 0 5/1? dut? 1 1 1 0 0 1 0 1 ?/1? dut? 1 1 1 0 0 1 1 0 7/1? dut? 1 1 1 0 0 1 1 1 8/1? dut? 1 1 1 0 1 0 0 0 9/1? dut? 1 1 1 0 1 0 0 1 10/1? dut? 1 1 1 0 1 0 1 0 11/1 ? dut? 1 1 1 0 1 0 1 1 1?/1? dut? 1 1 1 0 1 1 0 0 13/1? dut? 1 1 1 0 1 1 0 1 14/1? dut? 1 1 1 0 1 1 1 0 15/1? dut? 1 1 1 0 1 1 1 1 1?/1? dut? y
rev. 1.10 1? ?a? 1?? ? 011 rev. 1.10 17 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan the relationship between row and com digital dimming duty time is as follows: row ( n ) 10?4 s 1 / 1? dut? 3 / 1? dut? 4 / 1? dut? 5 / 1? dut? ? / 1? dut? 7 / 1? dut? 8 / 1? dut? 9 / 1? dut? 10 / 1? dut? 11 / 1? dut? 1? / 1? dut? 13 / 1? dut? 14 / 1? dut? 15 / 1? dut? 1? / 1? dut? ? / 1? dut? 1040 s co? ( n )
rev. 1.10 1? ?a? 1?? ? 011 rev. 1.10 17 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan keyscan the keyscan logic uses one, two or three of the ks0, ks1and ks2 logic outputs. an interrupt output that flags a key press is optional. the int flag can be read (polled) through the serial interface, allowing int/row15 to be used as a general purpose logic output or as a row open- drain driver. one small-signal diode is required per key switch when more than one key is connected to ks0, ks1 or ks2. the diodes prevent two simultaneous key switch depressions from shorting the com drivers together. for example, if sw1 and sw14 were pressed together and the diodes were not ftted, com1/ks0 and com2/ks1 would be shorted together and the led multiplexing would be incorrect. the keyscanning circuit utilises the com1/ks0 to com3/ks2 outputs high as the keyscan output drivers. the outputs com0 to com7 pulse low sequentially as the displays are multiplexed. the actual low time varies from 64s to 1024s due to pulse width modulation from 1/16th to 16/16th for dimming control. the led drive mode waveforms and scanning shows the typical situation when all eight led cathode drivers are used. the maximum of thirty-nine keys can only be scanned if the scan-limit register is set to scan the maximum ks0 to ks2. the keyscan cycle loops continuously over time, with all thirty-nine keys experiencing a full keyscanning debounce over 20ms. a key press is debounced and an interrupt issued if at least one key that was not pressed in a previous cycle is found to be pressed during both sampling periods. the keyscan circuit detects any combination of keys pressed during each debounce cycle (n-key rollover). the int output is active-low when the act bit of row/int set register is set to 0. the int output is active-high when the act bit of row/int set register is set to 1. com1/ks0 com2/ks1 com3/ks2 seg3/k1 seg4/k2 seg5/k3 seg6/k4 seg7/k5 seg8/k6 seg9/k7 seg10/k8 seg11/k9 seg12/k10 seg14/k12 seg15/k13 seg13/k11 = sw1 sw14 sw?7 sw? sw3 sw4 sw5 sw? sw7 sw8 sw9 sw10 sw11 sw1? sw13 sw15 sw1? sw17 sw18 sw19 sw?0 sw?1 sw?? sw?3 sw?4 sw?5 sw?? sw?8 sw?9 sw30 sw31 sw3? sw33 sw34 sw35 sw3? sw37 sw38 sw39
rev. 1.10 18 ?a? 1?? ? 011 rev. 1.10 19 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan keyscan timing the slave addresses are updated on the keyscan timing as shown : ks0 ks1 ks2 input mode com1/ks0 com2/ks1 com3/ks2 row0~15 1 cycle key scan period display period 1 frame ? slave address are updated slave address are updated slave address are updated ad ks0 ks1 input mode 2 cycle key scan period display period 1 frame ad ks0 ks1 ks2 input mode 3 cycle key scan period display period 1 frame slave address are updated ad ? ? ? ? ks0 ks1 ks2 input mode n cycle key scan period display period 1 frame ad com0/ad ks2 keyscan & int timing the key data is updated and the int function is changed for key s that have been pressed after 2 key-cycles. the int function is changed when the frst key has been pressed. when after all the key data has been read that clear s the key data ram and the int fag bit is set to 0, the int pin goes to low when the act bit of the row/int set register is set to 1. when after all the key data has been read that clear s the key data ram and the int fag bit is set to 0, the int pin goes to high when the act bit of the row/int set up register is set to 0. the int fag register is show n below. i 2 c bus d isplay data transfer format int fag register (address point at ?0h) d7 d6 d5 d4 d3 d2 d1 d0 int fag int fag int fag int fag int fag int fag int fag int fag the relationship between keyscan signal to the int signal time is show n below: 1. when a key is pressed on the ks0 row ks0 ks1 ks? press ke? int_flag 1 cycle 2 cycle int pin (active low) int pin (active high)
rev. 1.10 18 ?a? 1?? ? 011 rev. 1.10 19 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan 2. when a key is pressed on the ks1 row ks0 ks1 ks? press ke? int_flag 1 cycle 2 cycle int pin (active low) int pin (active high) 3. w hen a key is pressed on the ks2 row ks0 ks1 ks? press ke? int_flag 1 cycle 2 cycle int pin (active low) int pin (active high)
rev. 1.10 ?0 ?a? 1?? ? 011 rev. 1.10 ?1 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan k ey pressed during a keyscan cycle period. (i.e. the key is pressed on the ks2 row) the ke? data are updated when the interrupt asserted if required 1 c?cle ? c?cle 3 c?cle 4 c?cle press first ke? ke?scan int flag int pin (active low) int pin (active high) release ke? when after the all ke? data has been read: 1. clears the ke? data ra?. ?. the int flag bit is set to"0 3.the int pin goes to low when "act bit is set to 1. 4.the int pin goes to high when "act bit is ise to 0. 5 c?cle ? c?cle press second ke? ke? data are updated release ke? 7 c?cle key scan period key pressed during an led display period. (i.e. the key is pressed on the ks2 row) 1 c?cle ? c?cle 3 c?cle 4 c?cle press first ke? ke?scan int flag int pin (active low) int pin (active high) release ke? when after the all ke? data has been read: 1. clears the ke? data ra?. ?. the int flag bit is set to"0 3.the int pin goes to low when "act bit is set to 1. 4.the int pin goes to high when "act bit is ise to 0. 5 c?cle ? c?cle the ke? data are updated when the interrupt asserted if required ke? data are updated release ke? press second ke? key scan period
rev. 1.10 ?0 ?a? 1?? ? 011 rev. 1.10 ?1 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan key data memory C ram structure the ram is a static 16 x 3 -bits ram which stores key data which keys have been detected as key data by the key scanning circuit. each bit in the register corresponds to one key switch. the bit is set to 1 if the switch has been correctly key data since the last key data register read operation. reading the key data ram clears the key data ram after the key data has been read, so that future key presses can be identified. if the key data ram is not read, the key scan data accumulates. there is no fifo register in the HT16K33. key-press order, or whether a key has been pressed more than once, cannot be determined unless the all key data ram is read after each interrupt and before completion of the next keyscan cycle. after the all key data ram has been read, the int pin output is cleared along with the int fag status. if a key is pressed and held down, the key is reported as key data (and an int is issued) only once. the key must be detected as released by the keyscanning circuit before it is key data again. the key data ram is read only. a write to address 0x40~0x45 is ignored. it is strongly recommended that the key data ram is read only and should be started form address 0x40h only, the key data ram of address 0x40h ~0x45h should be read continuously and in one operation. there is a one-to-one correspondence between the key data ram addresses and the key data outputs and between the individual bits of a key data ram word and the key data outputs. the following shows the mapping from the ram to the key data output: row3~15 k1 k8 k9 k16 co?1/ks0 40h 41h co??/ks1 4?h 43h co?3/ks? 44h 45h i 2 c bus d isplay data transfer format data byte of i 2 c d7 d6 d5 d4 d3 d2 d1 d0 ks0 k8 k7 k? k5 k4 k3 k? k1 0 0 0 k13 k1? k11 k10 k9 ks1 k8 k7 k? k5 k4 k3 k? k1 0 0 0 k13 k1? k11 k10 k9 ks? k8 k7 k? k5 k4 k3 k? k1 0 0 0 k13 k1? k11 k10 k9
rev. 1.10 ?? ?a? 1?? ? 011 rev. 1.10 ?3 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan key matrix configuration an example of key matrix confgurations is shown below. when p ressing three or more times is assumed: a configuration example is shown below. in this configuration, 1 to 39 on switches can be recognised. ks0 ks1 ks2 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 = when pressing twice or more times is assumed: a configuration example is shown below. in this configuration, 0 to 2 on switches can be recognised. ks0 ks1 ks2 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 = in this confguration, pressing three or more times may cause the off switches to be determined as being on. for example, if sw2, sw4 are on and ks0 has been selected (high level) as shown below, sw3, in which current i1 is running is supposed to be detected to be on. however, since sw2 and sw4 are on, current i2 runs thus resulting in sw1 to be recognised as being on (ghost key). ks0 ks1 ks2 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 = sw1 sw3 sw? sw4 select i 1 i 2
rev. 1.10 ?? ?a? 1?? ? 011 rev. 1.10 ?3 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan if a diode is not available, not only the key data may not be read normally but the led display may be affected or the ics may be damaged. for example, if sw1 and sw2 are on and ks 0 has been selected (high level) as shown below, this will cause not only current i1 which is supposed to run but also a short-circuit current i2 of ks 0 to ks 1 to fow . it is possible that this will then cause the following t wo problems: (1) since the level to k2 is not correctly sent, the key data cannot be latched correctly. ( 2 ) since the short-circuited current (current i2) of ks 1 (high level) to ks 1 (low level) fows , the device may be damaged . ks0 ks1 ks2 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 = sw1 sw? select i 1 i 2 { non select key matrix combination with 28 pin package without int pin co?1/ks0 co??/ks1 co?3/ks? seg3/k1 seg4/k? seg5/k3 seg?/k4 seg7/k5 seg8/k? seg9/k7 seg10/k8 seg11/k9 seg1?/k10 seg14/k1? seg15/k13 seg13/k11 = with int pin co?1/ks0 co??/ks1 co?3/ks? seg3/k1 seg4/k? seg5/k3 seg?/k4 seg7/k5 seg8/k? seg9/k7 seg10/k8 seg11/k9 seg1?/k10 seg14/k1? seg13/k11 =
rev. 1.10 ?4 ?a? 1?? ? 011 rev. 1.10 ?5 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan key matrix combination with 24 pin package without int pin co?1/ks0 co??/ks1 co?3/ks? seg3/k1 seg4/k? seg5/k3 seg?/k4 seg7/k5 seg8/k? seg9/k7 seg10/k8 seg11/k9 seg1?/k10 = with int pin co?1/ks0 co??/ks1 co?3/ks? seg3/k1 seg4/k? seg5/k3 seg?/k4 seg7/k5 seg8/k? seg9/k7 seg10/k8 seg11/k9 = key matrix combination with 20 pin package without int pin co?1/ks0 co??/ks1 co?3/ks? seg3/k1 seg4/k? seg5/k3 seg?/k4 seg7/k5 seg8/k? seg9/k7 seg10/k8 = with int pin co?1/ks0 co??/ks1 co?3/ks? seg3/k1 seg4/k? seg5/k3 seg?/k4 seg7/k5 seg8/k? seg9/k7 =
rev. 1.10 ?4 ?a? 1?? ? 011 rev. 1.10 ?5 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan i 2 c serial interface the HT16K33 includes an i 2 c serial interface . the i 2 c bus is used for bidirectional, two-line com- com - munication between different ics or modules. t he two lines are a serial data line (sda) and a serial clock line (scl). both lines are connected to a positive supply via a pull-up resistor. when the bus is free, both lines are high. t he output stages of devices connected to the bus must have an open- drain or open-collector to perform a wired and function. data transfer is initiated only when the bus is not busy. data validity the data on the sda line must be stable during the high period of the clock. t he high or low state of the data line can only change when the clock signal on the scl line is low (see below). sda scl data line stable, data valid chang of data allowed start and stop conditions a high to low transition on the sda line while scl is high defnes a start condition. a low to high transition on the sda line while scl is high defnes a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in this respect, the start(s) and repeated start (sr) conditions are functionally identical. p s sda scl sda scl start condition stop condition byte format every byte put on the sda line must be 8-bits long. t he number of bytes that can be transmitted per transfer is unrestricted. e ach byte has to be followed by an acknowledge bit. d ata is transferred with the most signifcant bit (msb) frst. s or sr p or sr sda scl 1 2 7 8 9 ack 1 2 3-8 9 ack p sr
rev. 1.10 ?? ?a? 1?? ? 011 rev. 1.10 ?7 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan acknowledge each bytes includes eight bits is followed by a single acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge (ack) after the reception of each byte. the device that acknowledge must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. a master receiver must signal an end of data to the slave by generating a not-acknowledge (nack) bit on the last byte that has been clocked out of the slave. in this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. the master will generate a stop or repeated start condition. s 1 2 7 8 9 clk pulse for acknowledgement data output by transmiter data output by receiver scl from master acknowledge not acknowledge start condition slave addressing the HT16K33 device requires an 8-bit slave address word following a start condition to enable the device for a write operation. the device address words consist of a mandatory one, zero sequence for the frst four most signifcant bits (refer to the diagram showing the slave address). this is common to all led devices. the slave address input circuit is show n below. a2~a0 are set to 0, when a2~a0 are foating. a2~a0 are to 1, when a2~a0 are connected to an ad pin with a diode and resister. the slave address set is load ed into the HT16K33 at every frame. row?/a0 row1/a1 row0/a? a0 a1 a? ht1?k33 co?0/ad 39k*3 the slave address byte is the frst byte received following the start condition from the master device. the first seven bits of the first byte make up the slave address. the eighth bit defines whether a read or write operation is to be performed. when the r/ w bit are 1, then a read operation is selected. a 0 selects a write operation.
rev. 1.10 ?? ?a? 1?? ? 011 rev. 1.10 ?7 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan when an address byte is sent, the device compares the frst seven bits after the start condition. if they match, the device outputs an acknowledge on the sda line. 28-pin package: 1 1 1 0 a? a1 a0 r/w ?sb lsb slave address 24-pin package: 1 1 1 0 0 a1 a0 r/w ?sb lsb slave address 20-pin package: 1 1 1 0 0 r/w ?sb lsb slave address 0 0
rev. 1.10 ?8 ?a? 1?? ? 011 rev. 1.10 ?9 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan write operation byte write operation a b yte write operation requires a start condition, slave address with r/ w bit, a valid command code / register address, a data and a stop condition. slave address ack write command code ack p s 1 1 1 0 a? a1 a0 0 d15 d14 d13 d1? d11 d10 d9 d8 command byte received slave address ack write command / address b?te ack s 1 1 1 0 a? a1 a0 0 d15 d14 d13 d1? d11 d10 d9 d8 data code ack p d7 d? d5 d4 d3 d? d1 d0 1 b?te data command and single data byte received page write operation following a start condition and slave address with r/ w bit is placed on the bus and indicates to the addressed device that register address will follow and is to be written to the address pointer. the data to be written to the memory in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. a fter reaching the display memory location 0x0fh the pointer will reset to 0x00h (display memory). slave address ack write command / register address b?te ack s 1 1 1 0 a? a1 a0 0 d15 d14 d13 d1? d11 d10 d9 d8 data b?te ack p d7 d? d5 d4 d3 d? d1 d0 n b?tes data data b?te d7 d? d5 d4 d3 d? d1 d0 first b?te data ack data b?te d7 d? d5 d4 d3 d? d1 d0 second b?te data ? ack n data bytes received
rev. 1.10 ?8 ?a? 1?? ? 011 rev. 1.10 ?9 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan read operation byte read operation a b yte read operation requires a start condition, slave address with r/ w bit, a fx valid register address, slave address with r bit, a data and a nack signal and a stop condition. the byte reads command is not available for key data reading. slave address ack write command / register address b?te ack s 1 1 1 0 a? a1 a0 0 d15 d14 d13 d1? d11 d10 d9 d8 slave address read s 1 1 1 0 a? a1 a0 1 p ack data b?te d7 d? d5 d4 d3 d? d1 d0 1 b?te data p nack reading single data bytes from the HT16K33 page read operation in this mode, the master reads the HT16K33 data after setting the slave address. following a r/ w bit (=0) and acknowledge bit, the register address (an) is written to the address w pointer. next the start condition and slave address are repeated followed by a r/ w bit (=1). the data which was addressed is then transmitted. the address pointer is only incremented on reception of an acknowledge clock. the HT16K33 will place the data at address an+1 on the bus. the master reads and acknowledges the new byte and the address pointer is incremented to an+2. if the register address (an) is 0x00h ~ 0x0fh, after reaching the memory location 0x0fh, the pointer will be reset to 0x00h. the key data ram of address 0x40h~0x45h should be read continuously and complete d in one operation , so the key data ram of address should be started f rom 0x40h only. this cycle of reading consecutive addresses will continue until the master sends a nack signal and stop condition. slave address ack write command / register address b?te ack s 1 1 1 0 a? a1 a0 0 d15 d14 d13 d1? d11 d10 d9 d8 data b?te nack p d7 d? d5 d4 d3 d? d1 d0 n b?tes data slave address read s 1 1 1 0 a? a1 a0 1 p ack data b?te d7 d? d5 d4 d3 d? d1 d0 first b?te data ack data b?te d7 d? d5 d4 d3 d? d1 d0 second b?te data ack reading n data bytes from the HT16K33
rev. 1.10 30 ?a? 1?? ? 011 rev. 1.10 31 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan command summary name command / address option description def. d15 d14 d13 d12 d11 d10 d9 d8 displa? data address pointer 0 0 0 0 a3 a? a1 a0 {a0~a3} r/w five bits of immediate data ? bits a0 to a3? are transferred to the data pointer to defne one of sixteen displa? ra? addresses. if the displa ? data register address (an) is 0x00h ~ 0x0fh ? after reaching the memor ? location 0x0fh ? the pointer will reset to 0x00h 00h s?stem setup 0 0 1 0 x x x s {s} write onl ? defnes internal system oscillator on/off {0}:turn off s ? stem oscillator (standb ? mode) {1}:turn on s ? stem oscillator (normal operation mode) ?0h ke? data address pointer 0 1 0 0 0 k? k1 k0 {k0~k?} read onl ? three bits of immediate data ? bits k0 to k?? are transferred to the data pointer to defne one of six key data ram addresses. it is strongl ? recommended that the ke ? data ra? of address 0x40h~0x45h should be read continuousl ? and in one operation? so the ke? data ra? of address should be started at 0x40h onl? . if the ke ? data register address (an) is 0x40h ~ 0x45h ? after reaching the memor? location 0x45h? the pointer will reset to 0x40h 40h int fag address pointer 0 1 1 0 0 0 0 0 read onl ? defnes the int fag address, read int fag status. interrupt flag signal output. when an ? ke ? matrix ke? is pressed? after the completion of two key scan cycles, this int fag bit goes to a high level and remains at a high level until all ke? data has been read? ?0h displa? setup 1 0 0 0 x b1 b0 d {d} write onl ? defnes display on/off status. {0}: displa? off {1}: displa? on 80h {b1?b0} write onl ? defnes the blinking frequency {0?0} = blinking off {0?1} = ?hz {1?0} = 1hz {1?1} = 0.5hz note: if programmed command data is not defned, the function will not be af fected.
rev. 1.10 30 ?a? 1?? ? 011 rev. 1.10 31 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan name command / address option description def. d15 d14 d13 d12 d11 d10 d9 d8 row/int set 1 0 1 0 x x act row/ int {act? row/ int } write onl ? defnes int/row output pin select and int pin output active level status. {x 0}: int/row output pin is set to row driver output. {0? 1}: int/row output pin is set to int output? active low. {1? 1}: int/row output pin is set to int output? active high. a0h dimming set 1 1 1 0 p3 p? p1 p0 {p3~p0} write onl ? defnes the pulse width of row. {0?0?0?0}: 1/1?dut? {0?0?0?1}: ?/1?dut? {0?0?1?0}: 3/1?dut? {0?0?1?1}: 4/1?dut? {0?1?0?0}: 5/1?dut? {0?1?0?1}: ?/1?dut? {0?1?1?0}: 7/1?dut? {0?1?1?1}: 8/1?dut? {1?0?0?0}: 9/1?dut? {1?0?0?1}: 10/1?dut? {1?0?1? 0}: 11/1?dut? {1?0?1?1}: 1?/1?dut? {1?1?0?0}: 13/1?dut? {1?1?0?1}: 14/1?dut? {1?1?1?0}: 15/1?dut? {1?1?1?1}: 1?/1?dut? efh test mode 1 1 0 1 1 0 0 1 write onl ? holtek use onl ? d9h note: if a programmed command data is not defned, the function will not be af fected.
rev. 1.10 3? ?a? 1?? ? 011 rev. 1.10 33 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan HT16K33 operation fow chart a ccess procedures are illustrated below by means of fowcharts. initiali s ation power on end row/int output pin set int pin output level set dimming set internal s?stem clock enable blinking set display data rewrite C address setting start next processing displa? data ra? write address setting displa? on
rev. 1.10 3? ?a? 1?? ? 011 rev. 1.10 33 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan key data read no ?es start int flag bit =1 ? read ke? data next processing row/int select register set int / row bit=1? ?es no clear int flag and the ke? data ra? no ?es int pin bit =1 ? read ke? data next processing int pin is set to low level and clears the ke? data ra? no ?es int pin bit =0 ? read ke? data next processing int pin is set to high level and clears the ke? data ra? act bit is set to 0=? ?es no read ke? data next processing clear int flag and clears the ke? data ra? no
rev. 1.10 34 ?a? 1?? ? 011 rev. 1.10 35 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan application circuit 16*8 display application: (no int pin function and 13*3 key function) led matrix scl sda vdd vss ?cu vdd vss ht1?k33 vss 0.1uf co?0 co?1/ks0 co??/ks1 co?3/ks? co?4 co?5 co?? co?7 vdd row13/k11 row14/k1? row1?/k10 row11/k9 row10/k8 row9/k7 row8/k? row7/k5 row?/k4 row5/k3 row4/k? row3/k1 row?/a0 row1/a1 row0/a? row15/k13/int 39k*13 = r1 r? r3 r4 r5 r? r7 r8 r9 r10 r11 r1? r13 4.7k 4.7k r a0 r a1 r a? note: 1. if r a0 , r a1 and r a2 are open, the i 2 c slave address (a0~a2) is set to low. 2. if r a0 , r a1 and r a2 are 39k, the i 2 c slave address (a0~a2) is set to high. 3. if the key input is not used for led display, the resistor in series with the key input (r1~r13) can be omitted. 15*8 display application: (int pin function and 12*3 key function) led matrix scl sda vdd vss ?cu vdd vss ht1?k33 vss 0.1uf = co?0 co?1/ks0 co??/ks1 co?3/ks? co?4 co?5 co?? co?7 vdd row13/k11 row14/k1? row15/k13/int row1?/k10 row11/k9 row10/k8 row9/k7 row8/k? row7/k5 row?/k4 row5/k3 row4/k? row3/k1 row?/a0 row1/a1 row0/a? 39k*1? 4.7k 4.7k r1 r? r3 r4 r5 r? r7 r8 r9 r10 r11 r1? r a0 r a1 r a? note: 1. if r a0 , r a1 and r a2 are open, the i 2 c slave address (a0~a2) is set to low. 2. if r a0 , r a1 and r a2 are 39k, the i 2 c slave address (a0~a2) is set to high. 3. if the key input is not used for led display, the resistor in series with the key input (r1~r12) can be omitted.
rev. 1.10 34 ?a? 1?? ? 011 rev. 1.10 35 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan 12*8 display application: (no int pin function and 10*3 key function) led matrix scl sda vdd vss ?cu vdd vss ht1?k33 vss 0.1uf co?0 co?1/ks0 co??/ks1 co?3/ks? co?4 co?5 co?? co?7 vdd row11/k10/int row10/k9 row9/k8 row8/k7 row7/k? row?/k5 row5/k4 row4/k3 row3/k? row?/k1 row1/a0 row0/a1 39k*10 = r1 r? r3 r4 r5 r? r7 r8 r9 r10 4.7k 4.7k r a0 r a1 note: 1. if r a0 and r a1 are open, the i 2 c slave address (a0~a1) is set to low and a2 is always set to low. 2. if r a0 and r a1 are 39k, the i 2 c slave address (a0~a1) is set to high and a2 is always set to low. 3. if the key input is not used for led display, the resistor in series with the key input (r1~r10) can be omitted. 11*8 display application: (int pin function and 9*3 key function) led matrix scl sda vdd vss ht1?k33 co?0 co?1/ks0 co??/ks1 co?3/ks? co?4 co?5 co?? co?7 row11/k10int row10/k9 row9/k8 row8/k7 row7/k? row?/k5 row5/k4 row4/k3 row3/k? row?/k1 row1/a0 row0/a1 ?cu vdd vss vss 4.7k 0.1uf vdd 39k*9 = 4.7k r1 r? r3 r4 r5 r? r7 r8 r9 r a0 r a1 note: 1. if r a0 and r a1 are open, the i 2 c slave address (a0~a1) is set to low and a2 is always set to low. 2. if r a0 and r a1 are 39k, the i 2 c slave address (a0~a1) is set to high and a2 is always set to low. 3. if the key input is not used for led display, the resistor in series with the key input (r1~r9) can be omitted.
rev. 1.10 3? ?a? 1?? ? 011 rev. 1.10 37 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan 8*8 display application: (no int pin function and 8*3 key function) led matrix scl sda vdd vss ?cu vdd vss ht1?k33 vss 0.1uf co?0 co?1/ks0 co??/ks1 co?3/ks? co?4 co?5 co?? co?7 vdd row7/k8/int row?/k7 row5/k? row4/k5 row3/k4 row?/k3 row1/k? row0/k1 39k*8 = r1 r? r3 r4 r5 r? r7 r8 4.7k 4.7k note: 1. the i 2 c slave address (a0~a2) =000. 2. if the key input is not used for led display, the resistor in series with the key input (r1~r8) can be omitted. 7*8 display application: (int pin function and 7*3 key function) led matrix scl sda vdd vss ?cu vdd vss ht1?k33 0.1uf co?0 co?1/ks0 co??/ks1 co?3/ks? co?4 co?5 co?? co?7 row7/k8/int row?/k7 row5/k? row4/k5 row3/k4 row?/k3 row1/k? row0/k1 39k*7 = vss vdd r1 r? r3 r4 r5 r? r7 4.7k 4.7k note: 1. the i 2 c slave address (a0~a2) =000. 2. if the key input is not used for led display, the resistor in series with the key input (r1~r7) can be omitted.
rev. 1.10 3? ?a? 1?? ? 011 rev. 1.10 37 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan led matrix circuit co? 0 co? 1 co? ? co? 7 row 0 row 1 row ? row 3 row 4 row 5 row ? row 7 row 8 row 9 row 10 row 11 row 1? row 13 row 14 row 15
rev. 1.10 38 ?a? 1?? ? 011 rev. 1.10 39 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan package information 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.?5? D 0.300 c 0.01? D 0.0?0 c 0.49? D 0.51? d D D 0.104 e D 0.050 D f 0.004 D 0.01? g 0.01? D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.?4 b ?.50 D 7.?? c 0.30 D 0.51 c 1?.?0 D 13.00 d D D ?.?4 e D 1.?7 D f 0.10 D 0.30 g 0.41 D 1.?7 h 0.?0 D 0.33 0 D 8
rev. 1.10 38 ?a? 1?? ? 011 rev. 1.10 39 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.?5? D 0.300 c 0.01? D 0.0?0 c 0.598 D 0.?13 d D D 0.104 e D 0.050 D f 0.004 D 0.01? g 0.01? D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.?4 b ?.50 D 7.?? c 0.30 D 0.51 c 15.19 D 15.57 d D D ?.?4 e D 1.?7 D f 0.10 D 0.30 g 0.41 D 1.?7 h 0.?0 D 0.33 0 D 8
rev. 1.10 40 ?a? 1?? ? 011 rev. 1.10 41 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.?5? D 0.300 c 0.01? D 0.0?0 c 0.?97 D 0.713 d D D 0.104 e D 0.050 D f 0.004 D 0.01? g 0.01? D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.?4 b ?.50 D 7.?? c 0.30 D 0.51 c 17.70 D 18.11 d D D ?.?4 e D 1.?7 D f 0.10 D 0.30 g 0.41 D 1.?7 h 0.?0 D 0.33 0 D 8
rev. 1.10 40 ?a? 1?? ? 011 rev. 1.10 41 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan reel dimensions product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 package information 2 april 1, 2010 sop 20w, sop 24w, sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.? d ke? slit width ?.00.5 t1 space between flange ?4.8 +0.3/-0.? t? reel thickness 30.?0.?
rev. 1.10 4? ?a? 1?? ? 011 rev. 1.10 43 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan carrier tape dimensions carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 package information 3 april 1, 2010

sop 20w symbol description dimensions in mm w carrier tape width ?4.0 +0.3/-0.1 p cavit? pitch 1?.00.1 e perforation position 1.750.10 f cavit? to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavit? hole diameter 1.50 +0.?5/-0.00 p0 perforation pitch 4.00.1 p1 cavit? to perforation (length direction) ?.00.1 a0 cavit? length 10.80.1 b0 cavit? width 13.30.1 k0 cavit? depth 3.?0.1 t carrier tape thickness 0.300.05 c cover tape width ?1.30.1 sop 24w symbol description dimensions in mm w carrier tape width ?4.0+0.3 p cavit? pitch 1?.00.1 e perforation position 1.750.1 f cavit? to perforation (width direction) 11.50.1 d perforation diameter 1.55 +0.1/-0.00 d1 cavit? hole diameter 1.50 +0.?5/-0.00 p0 perforation pitch 4.00.1 p1 cavit? to perforation (length direction) ?.00.1 a0 cavit? length 10.90.1 b0 cavit? width 15.90.1 k0 cavit? depth 3.10.1 t carrier tape thickness 0.350.05 c cover tape width ?1.30.1
rev. 1.10 4? ?a? 1?? ? 011 rev. 1.10 43 ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan sop 28w (300mil) symbol description dimensions in mm w carrier tape width ?4.00.3 p cavit? pitch 1?.00.1 e perforation position 1.750.10 f cavit? to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavit? hole diameter 1.50 +0.?5/-0.00 p0 perforation pitch 4.00.1 p1 cavit? to perforation (length direction) ?.00.1 a0 cavit? length 10.850.10 b0 cavit? width 18.340.10 k0 cavit? depth ?.970.10 t carrier tape thickness 0.350.01 c cover tape width ?1.30.1
rev. 1.10 44 ?a? 1?? ? 011 rev. 1.10 pb ?a? 1?? ? 011 HT16K33 ram mapping 16*8 led controller driver with keyscan holtek semiconductor inc. (headquarters) no.3? creation rd. ii? science park? hsinchu? taiwan tel: 88 ?-3-5?3-1999 fax: 88?-3-5? 3-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. 3-?? yuanqu st.? nankang software park? taipei 115? taiwan tel: 88 ?-?-??55-7070 fax: 88?-?-??55-7373 fax: 88?-?-??55-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit a? productivit? building? no.5 gaoxin ? ?nd road? nanshan district? shenzhen? china 518057 tel: 8 ?-755-8?1?-9908? 8?-755-8?1?-9308 fax: 8?-755-8?1?-97?? holtek semiconductor (usa), inc. (north america sales offce) 4?7?9 fremont blvd.? fremont? ca 94538? usa tel: 1-510- ?5?-9880 fax: 1-510-?5?-9885 http://www.holtek.com cop?right ? ? 011 b? holtek se? iconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however ? holtek assumes no responsibilit ? arising from the use of the specifications described. the applications mentioned herein are used solel ? for the purpose of illustration and holtek makes no warrant? or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that ma ? present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or s ?stems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw .

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